Integrated circuits (ICs) are generally fabricated in parallel on a semiconductor wafer. For example, numerous ICs are formed on a wafer, such as a 300 mm wafer. Numerous processes are performed in forming the ICs. For example, the wafer may be subjected to repeated deposition, lithographic, etch, and planarization processes in forming the ICs.
In particular, planarization process is important for semiconductor processing. The purpose of planarization is to produce a planar surface, which is critical in semiconductor processing. One type of planarization process is chemical mechanical polishing (CMP).
However, due to underlying topography, conventional CMP processes have difficulties in producing planar surface. In particular, we have discovered that beveled wafer edge topographic effect causes pattern density impact which makes it difficult or impossible to produce a planar surface. Conventional CMP tools are unable to compensate for this pattern density impact. Non-planar surface causes defocus issues as well as excessive erosion, negatively impacting yields.
From the foregoing discussion, the present disclosure enables CMP processes to produce a planar surface.